Cypress Computer Hardware CY62147DV18 User Manual

CY62147DV18  
MoBL2™  
4-Mb (256K x 16) Static RAM  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
Features  
• Very high speed: 55 ns and 70 ns  
• Wide voltage range: 1.65V – 2.25V  
• Pin-compatible with CY62147CV18  
• Ultra-low active power  
input/output pins (I/O through I/O ) are placed in a high-im-  
0
15  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
— Typical active current: 1 mA @ f = 1 MHz  
Writing to the device is accomplished by asserting Chip En-  
able (CE) and Write Enable (WE) inputs LOW. If Byte Low  
— Typical active current: 6 mA @ f = f  
max  
Enable (BLE) is LOW, then data from I/O pins (I/O through  
• Ultra low standby power  
0
I/O ), is written into the location specified on the address pins  
7
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered 48-ball BGA  
(A through A ). If Byte High Enable (BHE) is LOW, then data  
0
17  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
17  
Reading from the device is accomplished by asserting Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
Functional Description[1]  
The CY62147DV18 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
8
15  
the truth table for a complete description of read and write  
modes.  
The CY62147DV18 is available in a 48-ball FBGA package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
7
6
A
A
A
A
256K x 16  
RAM Array  
5
4
3
2
I/O – I/O  
0
7
A
I/O – I/O  
8
A
A
A
15  
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Power  
Circuit  
-Down  
Note:  
Cypress Semiconductor Corporation  
Document #: 38-05343 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised February 26, 2004  
 
 
CY62147DV18  
MoBL2™  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.....................................................> 200 mA  
Storage Temperature ................................65°C to + 150°C  
Operating Range  
Ambient Temperature with  
Power Applied............................................55°C to + 125°C  
Ambient  
Supply Voltage to Ground  
Potential......................................–0.2V to + V  
Temperature  
[7]  
Device  
Range  
(T )  
V
CC  
+ 0.2V  
A
CC(MAX)  
CY62147DV18L Industrial –40°Cto+85°C 1.65V to 2.25V  
CY62147DV18LL  
DC Voltage Applied to Outputs  
[5,6]  
in High Z State  
..........................–0.2V to V  
+ 0.2V  
+ 0.2V  
CC(MAX)  
.....................0.2V to V  
CC (MAX)  
[5,6]  
DC Input Voltage  
Product Portfolio  
Power Dissipation  
Operating I (mA)  
CC  
V
Range (V)  
f = 1MHz  
f = f  
Standby I  
(µA)  
CC  
max  
SB2  
Speed  
(ns)  
[7]  
[7]  
[7]  
[7]  
Product  
Min.  
Typ.  
Max.  
Typ.  
Max.  
Typ.  
Max.  
Typ.  
Max.  
CY62147DV18L  
CY62147DV18LL  
CY62147DV18L  
CY62147DV18LL  
1.65  
1.8  
1.8  
2.25  
55  
1.0  
1.0  
2.0  
6
15  
10  
15  
10  
0.5  
0.5  
18  
12  
18  
12  
1.65  
2.25  
70  
2.0  
6
Electrical Characteristics Over the Operating Range  
CY62147DV18-55  
CY62147DV18-70  
[7]  
[7]  
Parameter Description  
Test Conditions  
Min. Typ.  
Max.  
Min. Typ.  
Max.  
Unit  
V
V
V
V
I
Output HIGH  
Voltage  
I
I
= –0.1 mA  
V
= 1.65V  
1.4  
1.4  
V
OH  
OL  
IH  
OH  
OL  
CC  
Output LOW  
Voltage  
= 0.1 mA  
V
= 1.65V  
0.2  
0.2  
V
CC  
Input HIGH  
Voltage  
V
V
=1.65V to 2.25V  
=1.65V to 2.25V  
1.4  
–0.2  
–1  
V
+ 0.2V 1.4  
V + 0.2V  
CC  
V
CC  
CC  
Input LOW  
Voltage  
0.4  
+1  
+1  
–0.2  
–1  
–1  
6
0.4  
+1  
+1  
V
IL  
CC  
Input Leakage GND < V < V  
Current  
µA  
µA  
mA  
IX  
I
CC  
I
I
OutputLeakage GND < V < V , Output Disabled  
Current  
–1  
OZ  
O
CC  
V
Operating f = f  
= 1/t  
V = 1.95V L  
CC(max)  
6
12  
8
12  
8
CC  
CC  
MAX  
RC  
Supply Current  
I
= 0 mA  
OUT  
LL  
CMOS levels  
V
= 2.25V L  
6
15  
10  
6
15  
10  
mA  
CC(max)  
I
= 0 mA  
OUT  
CMOS levels  
LL  
f = 1 MHz  
V
= 1.95V L  
1
1
1.5  
2
1
1
1.5  
2
mA  
mA  
CC(max)  
CC(max)  
LL  
= 2.25V L  
LL  
V
Notes:  
5.  
6.  
V
V
= –2.0V for pulse durations less than 20 ns.  
IL(min.)  
IH(max)  
=V +0.75V for pulse durations less than 20ns.  
CC  
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V  
, T = 25°C.  
CC  
CC(typ.)  
A
Document #: 38-05343 Rev. *B  
Page 3 of 11  
 
     
CY62147DV18  
MoBL2™  
Electrical Characteristics Over the Operating Range (continued)  
CY62147DV18-55  
CY62147DV18-70  
[7]  
[7]  
Parameter Description  
Test Conditions  
Min. Typ.  
Max.  
12  
8
Min. Typ.  
Max.  
12  
8
Unit  
I
Automatic CE CE > V 0.2V,  
Power-Down  
Current —  
V
=1.95V  
L
0.5  
0.5  
0.5  
µA  
SB1  
CC  
CC(max)  
V >V –0.2V,  
IN CC  
LL  
L
V <0.2V); f = f  
(Address and Data  
IN  
MAX  
V
=2.25V  
18  
12  
0.5  
18  
12  
CMOS Inputs  
CC(max)  
Only), f = 0 (OE,  
WE, BHE and BLE)  
LL  
I
Automatic CE CE > V – 0.2V,  
V
V
=1.95V  
=2.25V  
L
0.5  
0.5  
12  
8
0.5  
0.5  
12  
8
µA  
SB2  
CC  
CC(max)  
Power-down  
Current —  
V
V
>V –0.2Vor  
< 0.2V, f = 0  
IN  
IN  
CC  
LL  
L
18  
12  
18  
12  
CMOS Inputs  
CC(max)  
LL  
[8]  
Capacitance for all Packages  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
10  
Unit  
C
C
Input Capacitance  
Output Capacitance  
pF  
pF  
IN  
A
V
= V  
CC  
CC(typ)  
10  
OUT  
Thermal Resistance  
Parameter  
Description  
Test Conditions  
BGA  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit  
board  
75  
°C/W  
JA  
[8]  
Θ
Thermal Resistance  
(Junction to Case)  
10  
°C/W  
JC  
[8]  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
V
V
CC  
CC  
90%  
10%  
90%  
OUTPUT  
10%  
GND  
Rise Time = 1 V/ns  
Fall Time = 1 V/ns  
THÉVENIN EQUIVALENT  
R2  
30 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
R
TH  
OUTPUT  
V
Parameters  
1.80V  
13500  
10800  
6000  
Unit  
R1  
R2  
R
TH  
V
0.80  
V
TH  
Data Retention Characteristics (Over the Operating Range)  
[7]  
Parameter  
Description  
for Data Retention  
CC  
Conditions  
Min.  
Typ.  
Max. Unit  
V
V
1.0  
V
DR  
I
Data Retention Current  
V
V
= 1.0V CE > V – 0.2V,  
L
6
4
µA  
CCDR  
CC  
CC  
> V – 0.2V or V < 0.2V  
IN  
CC  
IN  
LL  
[8]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
t
R
RC  
Notes:  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05343 Rev. *B  
Page 4 of 11  
 
 
CY62147DV18  
MoBL2™  
wqewqewq  
Data Retention Waveform[9]  
DATA RETENTION MODE  
> 1.0 V  
V
V
CC(min)  
CC(min)  
V
V
CC  
DR  
t
t
R
CDR  
CE or  
BHE.BLE  
Switching Characteristics Over the Operating Range [10.]  
55 ns  
70 ns  
Parameter  
Read Cycle  
Description  
Read Cycle Time  
Min.  
55  
Max.  
Min.  
70  
Max.  
Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
55  
70  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
55  
25  
70  
35  
OE LOW to Data Valid  
[11]  
OE LOW to LOW Z  
5
10  
0
5
10  
0
[11, 12]  
OE HIGH to High Z  
16  
20  
16  
25  
[11]  
CE LOW to Low Z  
[11, 12]  
CE HIGH to High Z  
CE LOW to Power-Up  
CE HIGH to Power-Down  
55  
55  
70  
70  
PD  
BLE / BHE LOW to Data Valid  
DBE  
LZBE  
HZBE  
[11]  
BLE / BHE LOW to Low Z  
10  
10  
[11, 12]  
BLE / BHE HIGH to HIGH Z  
20  
25  
[13]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
55  
40  
40  
0
70  
50  
50  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
HA  
0
0
SA  
40  
40  
25  
0
45  
50  
30  
0
PWE  
BW  
BLE / BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
SD  
HD  
[11, 12]  
WE LOW to High-Z  
20  
25  
HZWE  
[11]  
WE HIGH to Low-Z  
10  
10  
LZWE  
Notes:  
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.  
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC(typ.)  
OL OH  
LZCE HZBE  
11. At any given temperature and voltage condition, t  
given device.  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
HZCE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
12.  
t
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedence state.  
HZOE HZCE HZBE  
HZWE  
13. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
Document #: 38-05343 Rev. *B  
Page 5 of 11  
 
         
CY62147DV18  
MoBL2™  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
PD  
HZCE  
t
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE/BLE  
t
LZOE  
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PU  
V
I
CC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
I
SB  
Notes:  
14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .  
IL  
IL  
15. WE is HIGH for read cycle.  
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.  
Document #: 38-05343 Rev. *B  
Page 6 of 11  
 
     
CY62147DV18  
MoBL2™  
Switching Waveforms (continued)  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CE  
tSCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
DATAIN  
DATA I/O  
NOTE  
t
HZOE  
Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATAIN  
DATA I/O  
NOTE  
t
HZOE  
Notes:  
17. Data I/O is high impedance if OE = V  
.
IH  
18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.  
IH  
19. During this period, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05343 Rev. *B  
Page 7 of 11  
 
     
CY62147DV18  
MoBL2™  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATAI/O  
DATAIN  
t
LZWE  
t
HZWE  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
WE  
t
SA  
tPWE  
tHZWE  
t
HD  
t
SD  
DATA I/O  
DATAIN  
tLZWE  
Document #: 38-05343 Rev. *B  
Page 8 of 11  
 
CY62147DV18  
MoBL2™  
Truth Table  
CE  
H
X
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs/Outputs  
High Z  
High Z  
Data Out (I/O –I/O  
Mode  
Deselect/Power-Down  
Deselect/Power-Down  
Read  
Power  
Standby (I  
Standby (I  
)
SB  
X
X
H
H
)
SB  
L
H
L
L
L
)
Active (I )  
CC  
O
15  
L
H
L
H
L
Data Out (I/O –I/O );  
Read (Lower byte only)  
Active (I )  
CC  
O
7
I/O –I/O in High Z  
8
15  
L
H
L
L
H
Data Out (I/O –I/O );  
Read (Higher byte only)  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
CC  
High Z  
High Z  
)
CC  
)
CC  
L
Data In (I/O –I/O  
)
)
CC  
O
15  
L
H
Data In (I/O –I/O );  
Write (Lower byte only)  
)
CC  
O
7
I/O –I/O in High Z  
8
15  
L
L
X
L
H
Data In (I/O –I/O );  
Write (Higher byte only)  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
Ordering Information  
Speed  
(ns)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
55  
CY62147DV18L-55BVI  
CY62147DV18LL-55BVI  
CY62147DV18L-70BVI  
CY62147DV18LL-70BVI  
CY62147DV18L-55BVXI  
CY62147DV18LL-55BVXI  
CY62147DV18L-70BVXI  
CY62147DV18LL-70BVXI  
BV48A  
BV48A  
BV48A  
BV48A  
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)  
Industrial  
Industrial  
Industrial  
Industrial  
70  
55  
70  
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm)  
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free  
48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free  
Document #: 38-05343 Rev. *B  
Page 9 of 11  
 
CY62147DV18  
MoBL2™  
Package Diagram  
48-Lead VFBGA (6 x 8 x 1 mm) BV48A  
51-85150-*B  
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and  
company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05343 Rev. *B  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
 
CY62147DV18  
MoBL2™  
Document History Page  
Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM  
Document Number: 38-05343  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
127482  
131009  
229908  
Description of Change  
06/17/03  
11/26/03  
See ECN  
HRT  
CBD  
AJU  
New Data Sheet  
*A  
Changed From Advance to Preliminary  
*B  
Changed From Preliminary to Final  
Added 70 ns speed bin  
Changed Vcc MAX spec from 2.20V to 2.25V  
Modified V spec on footnote #6 from V  
+ 0.5V to V  
+ 0.75V  
CC (MAX)  
IH  
CC (MAX)  
Changed I TYP values from 8 mA to 6 mA  
CC  
Changed I MAX values at Vcc (max) = 1.95V from 15 mA to 12 mA (L bin)  
CC  
and 10 mA to 8mA (LL bin)  
Changed I MAX values at Vcc (max) = 2.25V from 18 mA to 15 mA (L bin)  
CC  
and 12mA to 10 mA (LL bin)  
With modified V  
spec, changed I  
and I  
MAX values from 15 uA  
cc MAX  
SB1  
SB2  
to 18 uA (L bin) and 10 uA to 12 uA (LL bin)  
Modified input and output capacitance values  
Removed footnote #9 from earlier rev  
Removed MAX value for V  
DR  
Modified t  
from 20 ns to 16 ns  
HZOE  
Added Pb-free ordering information  
Document #: 38-05343 Rev. *B  
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